1. Technical Field
Embodiments of the present invention relate to semiconductor technology, and more particularly, to a column decoder that decodes column addresses and outputs column selection signals and to a semiconductor memory apparatus using the same.
2. Related Art
In general, semiconductor memory apparatuses include column decoders that decode a plurality of column addresses. A memory bank includes a plurality of segments each having a column decoder provided therein. Each column decoder includes a pre-decoder that divides the plurality of column addresses by a predetermined number and performs a pre-decoding operation on the divided column addresses, and a main decoder that decodes the column addresses which have been pre-decoded by the pre-decoder to output column selection signals. The segment is a divided memory region from which a one-bit data is read. The segment is the smallest unit into which the column address is divided.
The column decoder includes one pre-decoder and one corresponding main decoder.
FIG. 1 shows a conventional semiconductor memory having an eight-bank structure. In this structure, each of the eight banks has a half-bank structure, i.e., each bank is divided into two half banks. In FIG. 1, two different arrangements (typeA and typeB) of column decoders have been depicted.
In the case of the first arrangement typeA, one column decoder that outputs column selection signals to each of the half banks is arranged below each of the half banks. In the case of the second arrangement typeB, two column decoders are arranged between two half banks.
FIG. 2 depicts a typeA arrangement of column decoders with respect to memory banks, where one column decoder is arranged below each of the half banks. Assuming that each half bank includes eight segments Even0, Odd0, Even1, Odd1, Even2, Odd2, Even3, and Odd3 for an 8-bit prefetch, one main decoder and one pre-decoder are allocated to each of the segments.
The total number of pre-decoders in a memory apparatus is calculated as the number of half banks*the number of banks*the number of segments. For example, in a DDR3 in which there are sixteen data input/output buffers, the number of pre-decoders is equal to 2*8*8=128. As shown in FIG. 2, the number of main decoders is also 128.
FIG. 3 depicts a typeB arrangement of column decoders, where two column decoders are arranged between two half bank, each column decoder outputting column selection signals to each of the half banks. When the half bank includes eight segments for an 8-bit prefetch, one main decoder and one pre-decoder are allocated to each of the segments.
For example, in a DDR3 having sixteen data input/output buffers, the number of pre-decoders equal to the number of half banks*the number of banks*the number of segments (2*8*8=128). As shown in FIG. 3, the number of main decoders is also 128.
In a conventional semiconductor memory apparatus described above, when a bank is arranged as two half banks, a column decoder including a main decoder and a corresponding pre-decoder is provided for each of the half-banks. As a result, the area of the semiconductor memory apparatus dedicated to the decoders increases.
Further, in the conventional semiconductor memory apparatus having a quarter-bank structure, i.e., having one bank divided into four quarter banks, a column decoder including a main decoder and a corresponding pre-decoder is provided for each of the quarter-banks. Therefore, the number of main decoders and pre-decoders are twice as many as those in the half-bank structure, thus further increasing the area of the semiconductor memory apparatus.
As the number of banks of the semiconductor memory apparatus increases or banks are divided into sub-banks, the number of column decoders including main decoders and pre-decoders needed in the apparatus also increase. Further, as more column decoders are needed, more lines are also needed to connect to the pre-decoders and transmit the column addresses. Therefore, the area of the semiconductor memory apparatus increases, and, as a result, cell efficiency decreases.